| Collaborators |
- J.R. Huang, Department of
Electrical Engineering,
Tsing-Hua University, Hsinchu, Taiwan, ROC
- C.K. Ong, Department of
Electrical and Computer Engineering,
University of California, Santa Barbara, CA, USA
- Prof. K.T. Cheng, Department
of Electrical and Computer
Engineering, University of California, Santa Barbara, CA, USA
|
| This new FPGA-based
testetr is consisted of re-configurable hardware platform and a memory test-circuitry
compiler. The compiler takes user-specified parameters of memory under test
(such as the address and data bus widths, the clock rate, the march algorithms,
the data background, etc.) as input and produces the circuitry required
in the memory tester to functionally test the target memory chips. The test
circuitry, which is under a microcode-based architecture, is automatically
generated in the form of Hardware Description Language (HDL). The circuitry
is in turn automatically synthesized and implemented in the re-configurable
hardware platform. The proposed solution can tremendously reduce the memory
tester cost by providing hardware re-configurability to support a wide range
of memory chips. The synthesis framework for the tester not only enables
the automatic synthesis and mapping of the desired test circuitry into the
re-configurable tester but also guarantees that the tester can correctly
operate at the desired clock rate for various configurations. |
Chip Design Software Development
